The present invention relates to a circuit simulation for a reliability test on a model of a semiconductor integrated circuit.
To ship semiconductor integrated circuit devices having higher reliability, various reliability tests are conducted on the semiconductor integrated circuit devices before shipment of the products.
As the process is becoming finer, the influences of physical phenomena such as crosstalk, electromigration, hot-carrier degradation, power supply voltage drop (IR drop), and the like are becoming more conspicuous. As a result, the influence is exerted on the operation of a semiconductor integrated circuit device. The phenomena are caused by resistance in a power supply wire for supplying power in circuits, and the influence is exerted also by simultaneous switching of a plurality of circuits. When a voltage drop is large, the operation speed of the circuit decreases, and it causes erroneous operation of the circuit. Consequently, analysis of a voltage drop in the entire semiconductor integrated circuit device (entire chip) is being proposed (Japanese Unexamined Patent Publication No. 2006-277557).